1. Field of the Invention
The present invention relates to phase-locked loop systems and more particularly to digital phase-locked loop systems. Phase-locked loops are employed to generate a clock signal which is frequency and/or phase referenced to an external input signal. Phase-locked loop systems are used in many fields of communications, and are also employed in computer applications for data synchronization from peripheral sources. The present invention is particularly directed to the use of phase-locked loops for data separation in disk drive systems when reading data information which is interspersed with clock information.
FIG. 1 illustrates a typical computing system in which data is transmitted between a memory disk system 10 and a central processing unit (CPU) 12. A disk controller 14 is responsible for executing CPU initiated commands to the disk drive electronics. This includes writing properly formatted serial data to the disk and accurately recovering data from the disk. The computing system also typically includes an internal memory 16 and a direct memory access (DMA) control 18.
Data written onto a disk consists of logic ones and zeros which are written at a particular data, or bit cell, rate. In order to accurately read the data from the disk, the data rate of the signal being read must be known. This is facilitated by encoding the data which is written onto the disk so that the signals include clock information as well as data information. The embedded clock information is then employed to determine the data rate when signals from the disk are being read.
Data is most commonly encoded on a disk in modified frequency modulation (MFM) format. MFM is a digital signal, derived from the original non-return-to-zero (NRZ) data stream and a synchronous clock signal. The rules of MFM encoding are that each NRZ logic one causes a transition in the MFM signal at the center of the bit cell, and if an NRZ logic zero follows a logic one, the state of the MFM signal does not change. If a logic zero follows another logic zero, there is an MFM transition at the boundary between the two bit cells. An example of MFM coding is shown in FIG. 2. The NRZ data shown in FIG. 2A is comprised of a series of ones and zeros, each occupying a bit cell. A clock signal indicated in FIG. 2B defines the bit cells. The MFM signal shown in FIG. 2C may be generated from the NRZ data and clock signals by exclusive-oring the data and clock to form a phase encoded signal, and then dividing the number of transitions by two with a toggle flip-flop. It is only the MFM transitions, not their senses, that are essential to decoding. Typically, disk read electronics are employed so that the signal recovered from a disk is in the form of a narrow pulse for each MFM transition, as shown in FIG. 2D.
NRZ data may be recovered from MFM transitions as shown in FIG. 3. A window signal W, which is a delayed clock C, is generated and used to distinguish center-of-bit-cell (data) from boundary-of-bit-cell (clock) pulses. Each transition pulse T that occurs during the window latches a window extension signal E until the positive clock transition at the end of the bit cell. When E is high at the end of the window (negative transition of W) the NRZ data is a logic one; when E is low at that time, the NRZ data is a logic zero.
Ideally, the clock rate of data read from the disk is a known fixed value. Due to various factors, however, such is not the case, and the clock rate of the data must be determined by looking at the data itself and generating the clock and window signals at the appropriate frequency to track the data. The clock signal is recovered from the MFM data using a phase-locked loop driven by the transition pulses. The function of the phase-locked loop is to provide clock signals which are equal to the clock rate of the data being read. Although the clock rate has a known ideal value, the actual clock rate of the data will vary from the ideal due to several factors. These factors include variations in the speed that the data track moves past the read head of the disk drive, including both long-term and short-term disk speed variations, examples of which are eccentricity and warping of the circular data tracks. The purpose of the phase-locked loop is to generate clock signals which follow such data rate variations.
In addition to variations in the actual data rate, the timing of MFM pulses read from a disk deviate from the ideal due to high frequency noise at the read head from external sources and adjacent tracks and noise in the read electronics, and due to "peak shift", i.e., a shifting of bit position due to the magnetic field of adjacent bits of opposite polarity. The noise and peak shift results in random bit jitter (movement of transition pulses from their ideal positions) which is unrelated to variations in the data rate. Since the clock is recovered by reading the MFM pulses, the bit jitter can adversely affect the recovery of the clock signals.
2. Description of the Prior Art
To recover the original NRZ data and clock, a phase-locked loop (FIG. 4), driven by the transition pulses, reconstructs the clock signal, and the recovered clock and transition pulses are then decoded to give NRZ data. Typically, the clock signals are delayed a quarter of the clock period, and the delayed signal is used as a window to distinguish transitions occurring near the center of a bit cell from those occurring near the edge of each bit cell. Since only MFM transitions are available, the clock and data regions of the window signal (FIG. 8) cannot be uniquely identified with respect to the data stream. In practice MFM decoding is done using both signals as windows and the detection of a unique code is employed to determine which is the correct decoded MFM signal.
Ideally, each transition will occur precisely in the middle of the window signal. This will not always be the case, however, because of low frequency data rate variations which are not precisely tracked by the phase-locked loop and because of high frequency bit jitter. If the transition moves outside of the limits of the window, a read error will result. In order to accurately track the data rate of the MFM data transitions, the shift in the position of the transitions as a result of bit jitter should be ignored, whereas the shift in positions of the transitions as a result of change in the frequency of the data should be used to correct the frequency of the recovered clock and resultant window.
The most common prior art systems employ an analog phase-locked loop which incorporates low pass filtering in order to eliminate the effects of bit jitter on the generation of the recovered clock. Such a system is illustrated in FIG. 5. A voltage controlled oscillator (VCO) 20 is employed to generate the clock signals. The output of the VCO is applied to a phase detector 22, where its phase is compared to the phase of the input signal (transition pulses). The output of the phase detector 22 is a signal with low frequency components proportional to the phase error and high frequency components resulting from bit jitter. This signal is applied to a low pass filter and amplifier 24 which attenuates the high frequency components resulting from bit jitter. The output of the filter and amplifier is a control voltage which is applied to the VCO 20 to control its output frequency.
Although the analog phase-locked loop circuit of FIG. 5 generally has good performance, it has several disadvantages. Such analog circuits are difficult to design and build and require a large amount of circuit board space. Additionally, they require adjustments to properly align the circuits in the system, i.e., to adjust the VCO frequency and gains and currents of various components. These adjustments are expensive in terms of production costs since they result in lower throughput and require technician overhead during controller board manufacturing.
Digital phase-locked loop systems have been designed in the past. A typical system is illustrated in FIG. 6. In such systems, a variable multiple state component such as a counter or shift register 30 performs a function analogous to the VCO of the analog phase-locked loop. The shift register is driven by a sample clock 32. The carry output of the shift register provides an output signal of variable frequency which is used to toggle the recovered clock window signal. The output frequency of the shift register is varied by adding or subtracting states, as illustrated in FIG. 7. For example, the shift register 30 may have sixteen nominal states, as illustrated in FIG. 7B. In order to reduce the frequency of the window signal, one state is added, as illustrated in FIG. 7C, and in order to increase the frequency of the window signal, one state is subtracted, as illustrated in FIG. 7A.
A phase detector 34 is implemented with a microprocessor or logic array and determines when the transition pulses arrive with respect to the states of the shift register. The logic array incorporates an algorithm to determine frequency corrections as a function of the determination of the state of occurrence of the transition pulses. If a transition pulse does not arrive in the correct state, the phase detector provides an error signal on line 36 to alter the number of states, and thus the output frequency, of the shift register 30. Some prior art systems make only instantaneous corrections in the number of states per window as a function of the arrival of a transition pulse in that particular window. Other systems make both instantaneous corrections to a window based upon the occurrence of a transition pulse in that particular window as well as making long-term corrections based upon the occurrence of transition pulses with respect to previous windows.
The primary disadvantage of prior digital phase-locked loops is that they are first order, i.e., they do not incorporate the concept of a filter. As a result, bit jitter adversely affects the operation of the phase-locked loop. This is to be contrasted with higher order analog phase-locked loop systems in which the bit jitter is filtered out and does not affect the frequency tracking operation of the system. Since they are only first order, prior art digital phase-locked loops used for disk data separators have very low performance, i.e., high data recovery error rates.
A more complex digital phase-locked loop system is shown in U.S. Pat. No. 4,357,707 to Delury. In the system disclosed in this patent, adjustments in the length of each window are made in accordance with the arrival location of the current data pulse and immediately preceding data pulse. These adjustments are provided to correct the phase of the generated window signal with respect to the incoming data. In addition, adjustments are made to the nominal frequency of the window signal in order to track frequency variations in the data. Frequency changes are made when two consecutive data pulses arrive in a predetermined error region. Although this system provides advantages over simpler digital phase-locked loop systems, its performance still falls short of analog phase-locked loop systems.